Acoustic resonators are used in many applications that require a precisely controlled frequency, including but not limited to wireless devices such as mobile telephones, pagers, radio receivers, microwave satellite communication devices, and various types of handheld electronics. In these devices, it is often important for components to take up as little space as possible on a monolithic integrated circuit, for instance, particularly if the resonator is part of a monolithic integrated circuit.
Acoustic resonators are useful in many applications such as electronic filters. Filters that use piezoelectric materials are particularly useful for frequencies above about 300 MHz where a thin film, non-conductive piezoelectric resonator is commonly used. Piezoelectric resonators can be fabricated into compact, high quality filters that can be integrated into radio frequency CMOS circuitry, for instance. Bulk acoustic wave (BAW) resonators and circuits such as filters formed using BAW resonators can be very compact, have a low insertion loss and high power handling.
BAW resonators in a basic form comprise a piezoelectric material sandwiched between two opposing electrodes, and preferably these elements, which form the resonator, are acoustically isolated from the substrate in order to have a high Q bulk wave filter. Such resonators could be manufactured using normal CMOS and/or bipolar silicon processing techniques to be optimally commercially feasible in monolithic integrated circuits manufactured using these processing techniques. Acoustically isolating the resonator structure can be a challenge, however.
FIG. 7 shows a prior art bulk resonator 710 formed over an etch stop layer 726 and an etchable layer 727, which are deposited on a silicon wafer 711, by first forming a first electrode 712, coating a piezoelectric layer 713 over both the first electrode 712 and the wafer surface, and forming a second electrode 714 on the opposite side of the piezoelectric layer 713 relative to the first electrode 712. A number of vias 715A are then etched in the front face of the piezoelectric layer 713 exposing the wafer surface under the piezoelectric layer 713 to a selective etching process that selectively etches the wafer 711 below the piezoelectric layer 713, creating a cavity 716. An uncoupled resonator membrane 715 composed of the first and second electrodes 712, 714 and the piezoelectric layer 713 is thus formed. It is emphasized that the resonator membrane 715 is decoupled from the wafer 711 by etching using front openings 715A in a resonator membrane 715. Further details of such resonators and the related manufacturing process can be found in U.S. Pat. No. 6,355,498 to Chan et al., herein incorporated by reference.
There are several apparent problems with this technique. First, the vias 715A must be carefully placed and dimensioned to avoid the first and second electrodes 712, 714, as well as the edges of the piezoelectric layer 713. Otherwise the vias 715A might adversely affect the performance of the resonator 710. If the vias 715A are not located, dimensioned and formed within tight tolerances, they may remove a portion of the piezoelectric layer 713 between the electrodes 712, 714, resulting in the frequency performance of the resonator being affected. Second, in certain embodiments, additional layers of etch stopping or delimiting materials 726 add to the cost and complexity of fabrication. Third, because adjacent circuit elements on the same wafer might be present in monolithic integrated circuits, there are limitations on the type, use and timing of the cavity etching material. Fourth, the etching process must be done before a protective cap can be applied.
In prior systems that etch the cavity from the back side of the substrate using KOH for instance (see, WO 02-05425, for example), device density is low due to the angle the cavity side walls for relative to the surface of the substrate. Using this approach, the formation of the cavity and the decoupling of the resonator membrane are purportedly achieved by etching the cavity from the backside (the side opposite to the resonator membrane) of the substrate and through the entirety of the substrate. This process, however, means that the device density is low. The KOH etch process results in side walls that form an angle of 54.7° with the back surface of a silicon substrate. Therefore, a resonator having a 150 μm×150 μm length and width will result in cavities having a 450 μm×450 μm length and width on the backside of a 530 μm wafer, as identified in U.S. Pat. No. 6,384,697. Additionally, this approach requires that the cavity be aligned on one side with a resonator structure on the other side, and two-sided alignment of structures can be a challenge.